RTL Engineer Jobs in USA 2026 with Visa Sponsorship

Ready to architect chips powering the next generation of AI inference? DensityAI seeks an RTL Engineer for its Mountain View team. Visa sponsorship spans H-1B, O-1, TN, and E-3 categories. If cutting-edge silicon design excites you, this role offers genuine architectural ownership.

About the Role

You will own RTL design of digital blocks powering DensityAI’s AI accelerator. This includes defining microarchitecture and implementing SystemVerilog end-to-end. Additionally, you will drive trade-offs across pipelining, datapath, and power gating. You will also partner with DV, physical design, and DFT teams through tapeout.

This role covers everything from architecture definition through post-silicon bring-up. Compensation ranges between $215,000 and $300,000, plus equity grants.

About the Hiring Firm

DensityAI was founded by Ganesh Venkataramanan, who previously led Tesla’s Dojo supercomputer project. Co-founders Bill Chang and Ben Floering also came from Tesla’s engineering team. The company builds AI accelerators using a novel near-memory compute architecture. This design targets frontier-scale LLM inference, combining SRAM speed with HBM density.

DensityAI assembled roughly 20 former Tesla Dojo engineers during its early growth. The startup has attracted significant industry attention, including reported acquisition interest from Tesla itself.

Job Duties

• Own RTL design of digital blocks for the AI accelerator
• Translate architectural specs into efficient, synthesizable RTL
• Drive microarchitecture trade-offs for performance and power efficiency
• Partner with DV, physical design, and DFT teams closely
• Own block-level quality, including timing and CDC signoff
• Debug across simulation, emulation, and post-silicon bring-up

Job Requirements

• Strong digital design fundamentals and expert SystemVerilog skills
• 5+ years designing complex digital blocks taken to silicon
• Solid microarchitecture skills across pipelining and memory subsystems
• Strong synthesis and timing awareness, including STA and CDC
• Demonstrated collaboration across the full RTL-to-GDS flow
• Experience with AI accelerator design is a plus, not required

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Conclusion

This role suits engineers ready to shape cutting-edge AI chip architecture. With strong compensation and genuine founding-team pedigree, the opportunity carries real weight. For experienced RTL engineers seeking silicon design impact, DensityAI offers a compelling path.

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